ࡱ > R | bjbjqq x e e w $ P 9 4 m \ w ( @ @ @ v v v v v v v $ Ay { v u @ : @ @ @ v & Ww V V V @ H v V @ v V V f rh j T rg v mw 0 w g y| T y| ( rh rh ~ y| p @ @ V @ @ @ @ @ v v U N @ @ @ w @ @ @ @ y| @ @ @ @ @ @ @ @ @ : D D R 2 S D R A M c6RhVcSvF P G A S[s sh \ "imo ( -NWSgNyb'Yf[ {:gNOo`]zf[bVnWS l 4 1 0 0 0 1 ) Xd: D D R 2 S D R A M /f,{NNS Ppenc OsTekR`:gX[PhVNvQ'Y[ϑ0ؚsTo}Yv|Q['`_0RN^l^(u0D D R 2 Grvc6R:N YBg:NN㉳QD D R 2 GrvqRSR(WN~NvQyrpT]\O:g6RvW@x NcQN Ny{Sv]\OAmzVۏ~Q勧c6RhVv;`SO0F P G A hVNv_RMSel0vQ-NelǑ(uV e r i l o g H D L lxNc g^ND D R 2 c6RhVI P o8hvKmՋs^SǏM o d e l S i m oN[D D R 2 Nw!jWKmՋeTQO(uQ u a r t u s I I oNvL]eQ_;RgN]wQS i g n a l T a p I I bSF P G A _Sg[eOS0 _Sg Nv~ghfD D R 2 GrRYSbRvQ_ N g3z[vQpenc(WSles2 0 0 M H z NQeQpencTQpenc N0EeD D R 2 c6RhV0RBlNc6RhVcS{US0]\O3z[0y i'`:_0 sQ.͋F P G A hVN; D D R 2 S D R A M cS; GrqR -NVR{|ST N 4 7 e.shƋxA D e s i g n and Implementation of DDR2 SDRAM Controller Interface on FPGA Wang Meng, Jiang Feng, Xie Haolan ( Central South University of Forestry and Technology, Changsha 410001,China) Abstract:DDR2 SDRAM, as the second generation dynamic random memory, is applied widely because of its large capacity, high speed and good compatibility. Because the control of DDR2 chip is more complex, a simplified work flow chart based on its characteristics and working mechanism is proposed to solve the problem of chip driver and f u n c t i o n v e r i f i c a t i o n f o r D D R 2 . F u r t h e r m o r e , t h e o v e r a l l d e s i g n v e r i f i c a t i o n m e t h o d a n d p i n a s s i g n m e n t o f D D R 2 c o n t r o l l e r i n F P G A d e v i c e a r e g i v e n . A t e s t p l a t f o r m o f t h e D D R 2 c o n t r o l l e r I P c o r e i s b u i l d u s i n g V e r i l o g H D L l a n g u a g e i n t h e v e r i f i c a t i o n m e t h od ,which test successfully the simulation model of DDR2 by Modelsim software. And then the real-time signals in FPGA evaluation board are captured by adopting SignalTapII Logic Analyzer embedded in QuartusII software. The verification results in evaluation board show that the initialization of DDR2 chip is successful; pins of DDR2 chip have stable read and write data; the write data and read data are consistent under the dual edges clock with 200MHz frequency. Therefore, the DDR2 controller meets design req u i r e m e n t s , a n d i t h a s s i m p l e i n t e r f a c e , b e t t e r s t a b i l i t y a n d t r a n s p l a n t a b l i t y . K e y w o r d s : F P G A d e v i c e ; D D R 2 S D R A M i n t e r f a c e s ; c h i p d r i v e r ; v e r i f i c a t i o n 0 _ @wƖb5ub/gvSU\^(uNQ]bl(uWvVb_Yt0Ɖvc5uP[NT[X[PhVv^BlegؚSNX[PhVv^/fQ[|~'`vsQ.V }KN N0D D R / D D R 2 / D D R 3 |RvS D R A M R`X[PhV1uN(WevcklۏLQd\ONvQؚ0'Y[ϑ0ЏL3z[Sؚ'`NkI{Opb:NNvMRX[PhVv;NAm01uND D R 2 vd\Oe^_ YBgۂ;R b[^vD D R c6RhV5u~g_Nkryr0Vdk_YF P G A SFUWNvQSzGrv0N[olxNDnYNuYؚseOSvƖbP L L vs/ecS S T L 1 . 8 V 0T T L 3 . 3 V I{Y5us^vSzI / O zS&^veޏcvVb_Se^~_goN]wQI{ND D R 2 / D D R 3 X[Pc6RhVI P 8h0vQ-NNA L t e r a lQSvX[Pc6RhVHes gؚ0O(u:N^l(u7bS NF P G A Gr_N(uNޏcD D R 2 / D D R 3 _vRSX[PhVv]\O:g6RsSS[sD D R c6RhVv0 WN NRg,gexvzN D D R 2 S D R A M v]\OStSc6RhVI P 8h㉳QeHh, Ǒ(ua l t e r a lQSvD D R 2 I P 8h(Ws:WSz5RGrF P G A -N[sD D R 2 v^)R(uL]eQ_;RgNS i g n a l t a p I I oN]wQN2 0 0 M H z Sle;NNvlxNKmՋ~g0 D D R 2 v]\O:g6R D D R 2 vRYS D D R 2 S D R A M R5uT_{ cgqĉ[vek[bRYS0(WRYSvǏz-N^la[!j_[X[hVM R TibU\!j_[X[hVE M R vMn0ǏRYSSN[b[C A S ^ߏzS^zS{|WQqRRGr Nzc5u;O D T