ࡱ > I K H M | } ~ 2 3 ; M O Q _ R H` bjbj Q b b - t ~ ( Z D G z z z z # V$ 4 $ F F F F F F F $ dJ M ~ F $ # " # " $ $ F z z ZG 0 0 0 $ 8 z z F 0 $ F 0 0 A /C z g } , h wB F pG 0 G B M . LN ( /C /C M (N $ CC \ $ $ 0 $ $ $ $ $ F F 0 $ $ $ G $ $ $ $ LN $ $ $ $ $ $ $ $ $ , : : WN_gY8h|~-NeWv㉳QeHh sOs^1 , ညΞ1 2 , hgec1 ထNu1 [1 1 . Nwm'Yf[ _5uP[xvzN _S-N_, Nwm2 0 0 0 7 2 ; 2 . :g5u]zNꁨRSf[b, Nwm2 0 0 0 7 2 Xd @wƖb5uvƖb^N'`v NeSU\GrvR]~SvASR%N͑R&^egvcbevzQ0_gY8hR`gg/fvMRxvzNORv;NAmeT0S O C |~S_-NT Ne;RS g N*NYthVYc6R;`~vQ[YthVRYtI{_r`_gY8hR`ggYǏMNO Nc6R;`~vYthVseg0RMNORvvv0_gY8hWvYthVT;`~eW㉳QeHhdkeHh(WVQ^\N!kcQSNЏ(u(W_gY8hR`( D F S ) ggS_-N0vMRKbc~zYeg:_Rv͑'`Vdk_gY8hWvYthVT;`~eW㉳QeHh\ g^8^}Yv^(uMRof0勹eHhǏ(WYthVTA M B A ;`~KNmRF I F O NS NN YBgv{l0RmdN3z`Tck8^Ovvv0 g~ǏNwSsNaYthVv]\Osn OOS0f勹eHh(W_gY8hR`gg-NЏ(u0 sQ.͋Ɩb5uA M B A _gY8hF I F O -NVR{|S T N 4 7 e.shƋxA A m e t h o d t o s o l v e t h e f r e q u e n c y i n c o n s i s t e n t b e t w e e n h e t e r o g e n e o u s m u l t i c o r e p r o c e s s o r a n d s y s t e m b u s W A N G W e i P i n g 1 , H U Y u e - L i 1 2 Y A N G W e n R o n g 1 H U Y u n S h e n g 1 Z U A n J i 1 ( 1 R e s e a r c h a n d D e v e l o p C e n t e r o f M i c r o e l e c t r o n i c s , S h a n g h a i U n i v e r s ity, Shanghai 200072, China 2 HYPERLINK "http://www.shu.edu.cn/en/SchoolMechatronics.htm"School of Mechanical and Electronic Engineering and Automation, Shanghai University, Shanghai 200072, China) Abstract: With the development of integration and performance of SOC, SOC has reached a hundred watt power consumption. Power consumption challenges increasingly prominent. Heterogeneous multi-core architecture used dynamic frequency is the main direction of the of low power consumption . There is only one processor to control the bus on the SOC system at the same,.while other processor processing wait state. heterogeneous multi-core architecture can reduce the dynamic frequency of processor which not control bus to achieve the purpose of reducing power consumption. This paper puts forward a clock domain processor and a heterogeneous multi-core bus field cross scheme, this scheme is put forward for the first time in the w o r l d 0i t c a n b e u s e d i n h e t e r o g e n e o u s m u l t i c o r e d y n a m i c f r e q u e n c y m o d u l a t i o n ( D F S ) a r c h i t e c t u r e . T h e i m p o r t a n c e o f h a n d h e l d d e v i c e s a r e m o r e a n d m o r e e m p h a s i s o n p o w e r c o n s u m p t i o n , s o t h e h e t e r o g e n e o u s m u l t i - c o r e p r o c e s s o r a n d b u s i n t h e f i e l d o f c r o s s clock domain solution will have a very good application prospect. This scheme by adding FIFO and some complex algorithm between the processor and the AMBA bus, to eliminate the metastable state and normal communication purposes. Finally, the simulation shows that the frequency adjustable processor can meet the transmission protocol. It is proved that this system can use in heterogeneous multi-core architecture in dynamic frequency. Keywords: Integrated circuit design; AMBA; Heterogeneous multi-core;FIFO E E A C C : T N 4 7 P A C C : A 0 _ ExƖb5ub/g Nvl@wid\[_ؚSU\ُyR\SNc~0R2 0 2 6 t^0N_vƖb5u@w͑:_Nf\byTf_v^eg[bЏ{NR06qS_Ɩb5ub/gSU\0RmN_s|6kbyT^]~ N/f/U NQvvh0s(WvC P U SFUeg͑ƉR\vRcep[fSpϑNOvC P U SN0Rfؚv]\Os0R N,R:N$NyR`RTY`R0R`R/fcGr(W]\Or`eM O S {YNSr`@bNuvR[;N/f1uw5uAmNuvwRNS _sQ5uAm_wvR` _sQR$NR~b0Y`RSy:Nl2R/fc5uYN No;mr`eSOPNg{o5uAmha^ogo5uAmN