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Arbitrary waveform generators typically employ direct digital waveform synthesis techniques to generate arbitrary waveforms. However, when utilizing this technology to achieve a variable sampling rate functionality, adjustments to the clock frequency can introduce hard-to-filter image frequencies and increase the complexity of hardware implementation. To address these issues, research was conducted on an arbitrary multiple resampling method based on the Farrow architecture. A parallel implementation of a 32-channel arbitrary resampling system was designed and realized on an FPGA under a fixed clock drive. Additionally, a solution for managing the accumulation of quantization errors in the logical implementation was proposed and implemented. Experimental results demonstrated that the system achieved sampling rate conversion from 1KSPS to 6GSPS under a fixed clock frequency of 187.5 MHz and effectively addressed waveform distortion issues caused by quantization error accumulation during long-term operation.