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A low power deep separable convolution accelerator kernel based on FPGA is designed. According to the commonality of PW convolution and DW convolution calculation, a fixed multiplicative array is used to realize the two convolution calculation structures by changing the feature and weight input data stream, so as to maximize the utilization of DSP. In order to solve the problem that the sign bit may overflow in 8-bit asymmetric quantization, the double multiplier structure is repackaged by using the sign bit processing method. The parallelism of data processing in each cycle is guaranteed by the 7-level pipelining structure in the layer. Successfully deployed the accelerator structure on the Zynq UltraScale+ series FPGA; The experimental results show that the proposed acceleration structure can improve the inference speed of the network and reduce the dependence of on-chip resources and the overall power consumption. The average throughput of the original MobilenetV2 on the proposed FPGA accelerator is as high as 130.6GOPS and the overall power consumption is only 4.1w, which meets the requirements of real-time edge computing. Compared with other hardware platforms, the energy efficiency ratio is significantly improved; Compared with the same type of accelerator on FPGA, it has advantages in performance density (GOPS/LUT), power efficiency (GOPS/W) and DSP efficiency (GOPS/DSP).