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In the back-end process of digital chip design, the placement of macros and standard cells is a time-consuming task, and providing solutions quickly and effectively through machine learning can speed up the chip development cycle and reduce the risk caused by manual placement. However, the placement problem is a multi-objective optimization problem, and most of the current methods focus on maximizing the reduction of line length under meeting various indicators, which has been exchanged for the reduction of clock delay, ignoring that other indicators still have room for decline, such as good congestion indicators are conducive to reducing chip heat dissipation and power consumption; To solve the above problems, a new deep reinforcement learning framework with intensive reward function is designed, which maps congestion information to images, gives a new feature embedding model to extract the global information of the layout at multiple scales, introduces the connection relationship of the graph attention network to capture the netlist, and updates the policy function with the Advantage Actor Critic (A2C) algorithm to realize the automatic placement of the digital landscape. The effectiveness of the proposed method is verified on the public digital chip netlist benchmark.