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The router is a key component of the on-chip network, and its performance has an important impact on the performance of the whole network. For the functional verification of the network-on-chip router, a verification platform based on the universal verification methodology (UVM) is constructed by using SystemVerilog and automation scripts to simplify the verification process. In the verification platform, the router's functionality is adequately verified by dividing multiple agents into sending to each of its ports constrained random excitation and directional tests, and creating multiple independent test cases to fully verify the functionality of the router. The verification process is quantified by applying coverage-driven strategies. Coverage groups and cross-coverage groups are written to collect coverage data according to the design requirements of the router. This verification platform has been used in the verification of AI chips, and both the components in the platform and the components and test cases in the platform can be reused at a higher level. In addition, the goal of 100% functional coverage and 95.6% code coverage is achieved through the simulation of VCS and Verdi.