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基于PCIE總線(xiàn)的大數據通信傳輸時(shí)延控制系統設計
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廣東理工職業(yè)學(xué)院

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Design of transmission delay control system for big data communication based on PCIE bus
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    摘要:

    在大數據傳輸中,當網(wǎng)絡(luò )流量過(guò)大或網(wǎng)絡(luò )拓撲復雜時(shí),可能會(huì )出現網(wǎng)絡(luò )擁塞的情況,導致通信傳輸時(shí)延的增加,為了優(yōu)化通信網(wǎng)絡(luò )的數據傳輸效率,設計基于PCIE總線(xiàn)的大數據通信傳輸時(shí)延控制系統。在PCIE總線(xiàn)核結構下設計大數據收發(fā)器、通信轉換模塊與通信中斷控制器,搭建時(shí)延控制終端,聯(lián)合大數據通信寄存器與時(shí)延狀態(tài)估計器,實(shí)現傳輸時(shí)延控制硬件系統的設計。在通信數據相空間內,計算傳輸時(shí)延量的具體數值水平,完成對大數據通信傳輸時(shí)延的預測。根據大數據通信序列定義條件,得到與通信傳輸時(shí)延狀態(tài)相關(guān)的反饋信息,并以此為基礎,確定具體的控制方案,完成基于PCIE總線(xiàn)的大數據通信傳輸時(shí)延控制系統設計。實(shí)驗結果表明,PCIE總線(xiàn)控制系統的應用可將大數據通信時(shí)延控制在0-0.20ms范圍之內,不會(huì )因時(shí)延過(guò)大造成數據信息瞬時(shí)響應速率下降的問(wèn)題,且數據傳輸丟包率低于%,符合實(shí)際應用需求。

    Abstract:

    In big data transmission, when the network traffic is too large or the network topology is complex, network congestion may occur, leading to an increase in communication transmission delay. In order to optimize the data transmission efficiency of the communication network, a big data communication transmission delay control system based on PCIE bus is designed. Design a big data transceiver, communication conversion module, and communication interrupt controller under the PCIE bus core structure, build a delay control terminal, and combine the big data communication register and delay state estimator to achieve the design of the transmission delay control hardware system. Calculate the specific numerical level of transmission delay in the communication data phase space, and complete the prediction of big data communication transmission delay. Based on the defined conditions of the big data communication sequence, feedback information related to the communication transmission delay state is obtained, and based on this, specific control schemes are determined to complete the design of the big data communication transmission delay control system based on the PCIE bus. The experimental results show that the application of the PCIE bus control system can control the delay of big data communication within the range of 0-0.20ms, without causing a decrease in the instantaneous response rate of data information due to excessive delay, and the packet loss rate of data transmission is less than%, which meets the practical application requirements.

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焦冬艷.基于PCIE總線(xiàn)的大數據通信傳輸時(shí)延控制系統設計計算機測量與控制[J].,2024,32(10):118-124.

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  • 收稿日期:2023-09-14
  • 最后修改日期:2023-10-24
  • 錄用日期:2023-10-24
  • 在線(xiàn)發(fā)布日期: 2024-10-30
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