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In order to address the issue of excessive latency in multiplication operations of high-performance RISC-V processors, improvements have been made to the basic multiplier by modifying the base-4 Booth encoding and Wallace tree architecture. A novel approach based on signed compensation for base-4 Booth encoding and an alternation of 3-2 compressors and 4-2 compressors for the Wallace tree structure is proposed. The base-4 Booth encoding with signed compensation reduces the number of partial products and decreases the power consumption caused by sign bit carry flipping. The improved Wallace tree structure reduces the clock cycles required for partial product accumulation, shortening the critical path of the multiplier and reducing the execution delay of multiplication instructions. The functionality of the improved multiplier was verified using VCS simulation, and its performance was evaluated through board-level testing. The results demonstrate that the proposed multiplier functions correctly. Compared to the PicoRV32, the clock cycles required for executing integer multiplication instructions were reduced by 88.2%. The Dhrystone score increased by 71.7%, while power consumption decreased by 4.9%.