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DDR SDRAM is an important component of FPGA boards, and its reliability and bandwidth determine whether the device can function properly. To verify that the performance of the DDR SDRAM meets expectations, a DDR SDRAM test platform based on FPGA is developed. The platform incorporates a tester IP core, which is based on a DDR SDRAM controller and has the capability to verify data and measure bandwidth. Tcl scripts are used to control the tester IP core, including setting test parameters, managing test processes, and retrieving test results. Additionally, a graphical interface program is designed using the PyQt5 development library in Python, which generates and executes corresponding Tcl scripts based on user input. As a result, a DDR SDRAM testing platform is implemented that is both user-friendly and flexible in terms of the testing process, while also providing automatic results output. Test results demonstrate that the platform accurately tests DDR SDRAM and outputs statistical results. Moreover, compared to the example design of MIG, the testing platform includes bandwidth testing, result statistics, and automatic control functions, ultimately reducing FPGA resource usage by 30% and cutting test time by more than 70%.