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In order to reduce the influence of RF singal on the performance of attenuation circuit in transceiver component,the attenuator can better adapt to the application requirements of high integration beamforming circuit in phased array system. This paper presents a 6-bits digital attenuator featuring small phase variation and low insertion loss using a 55-nm CMOS technology. The digital attenuator had a dynamic attenuation range from 0 to 31.5dB with a step resolution of 0.5dB. In order to reduce the insertion loss, the floating gate and floating body is adopted in the NMOS switch. In addition, low phase variation is achieved by using inductance compensation as well as capacitance compensation network. The simulation results shows that the insertion loss is less than -7 dB, while achieving an ±3°phase variation for all attenuation state in the frequency range of 10~ 26 GHz. The input and output reflection wave are less than -10dB. The RMS(Root Mean Square) attenuation error is less than 0.8dB. The total chip size excluding pads is 0.36mm× 0.16mm (mm2).