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A compact 16-bit precision sine lookup table (ROM) for direct digital frequency synthesizer (DDS) is designed by combining the improved sunderland algorithm with QE-ROM technology, and the system-level simulation and hardware description language (Verilog HDL) implementation of the designed sine lookup table algorithm are carried out. The designed sine lookup algorithm is simulated and implemented in hardware description language (Verilog HDL), and the overall algorithm function and performance are finally verified on FPGA; a multi-channel 16-bit output digital-to-analog converter (DAC) is fabricated based on AD5360 chip, and a step-down voltage regulator LM317 and LM337 are equipped to realize a power supply that can convert 220V industrial frequency to ±9V and 3.75V required by DAC. 3.75V power supply. The test results show that the designed sinusoidal lookup table algorithm occupies only 8576 bits of storage space while achieving 16-bit accuracy. The sine data optimization algorithm used saves 99.2% of resources compared to the conventional DDS sine waveform generator, achieves a compression ratio of 122:1, and effectively reduces the chip area and power consumption of the DDS.