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具備HART主站功能的模擬量采集模塊設計
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國核自?xún)x系統工程有限公司

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TP273

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國家電力投資集團(20RD009A)


Design of an Analog Acquisition Module with HART Master Function
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    摘要:

    設計基于CPU+FPGA架構的具備快速HART主站功能的多通道模擬量采集模塊;采集模塊的CPU與FPGA通過(guò)PCIe總線(xiàn)通信;FPGA通過(guò)隔離的SPI總線(xiàn)控制8路模擬量采集通道,并與兩路協(xié)議轉換芯片通信;單個(gè)協(xié)議轉換芯片實(shí)現一路SPI與四路UART的轉換,與四路HART MODEM通過(guò)UART接口通信;HART信號通道與模擬量采集通道一一對應,HART信號通過(guò)耦合模塊與模擬量信號在濾波模塊和保護電路之間疊加;模擬量輸入信號,經(jīng)過(guò)通道保護電路和濾波模塊后到達模擬量轉換模塊,進(jìn)行模數轉換;通過(guò)使用FPGA和協(xié)議轉換芯片,實(shí)現了8個(gè)模擬量采集通道的并行采集處理,實(shí)現了HART通道串行通信的并行工作;在CPU中運行兩個(gè)獨立線(xiàn)程,各自負責一片協(xié)議轉換芯片下的四路HART通信,四路HART通信以循環(huán)發(fā)送和循環(huán)接收的方式工作;并行工作的方式提高了模擬量采集的速率,減少了HART通信的等待時(shí)間,提高了HART通信的效率;模塊通道之間相互隔離,降低了通道間故障相互影響的概率,提高了模塊的可靠性;模塊支持4~20mA電流信號和±5V、±10V電壓信號采集,采集精度0.1%,電流采樣電阻250歐姆,通道間隔離電壓可達1000VDC。

    Abstract:

    A multi-channel analog acquisition module which can work as a HART master is designed based on the CPU+FPGA architecture. The CPU and the FPGA of the acquisition module communicates with each other through the PCIe bus. The FPGA controls eight analog acquisition channels through the isolated SPI bus and communicates with two protocol conversation chips. The chip converts one-channel SPI to four-channel UART and communicates with four-channel HART MODEMs through the UART interface. One HART channel corresponds with one analog acquisition channel. HART signals are superimposed with the analog signals between the filtration module and the protection circuit through the coupling module. The analog input signals pass through the channel protective circuit and the filtration module and reach the analog conversion module where analog signals are converted into digital signals. The FPGA and the protocol conversion chips help realize the parallel processing of eight analog acquisition channels and the concurrent working of HART channel serial communication. There are two separated threads in the CPU, each responsible for four channel HART communication which sends and receives signals periodically. The concurrent working method improves the speed of analog acquisition, reduces the delay time and increases the efficiency of the HART communication. The isolated-channel design reduces the impact of fault channels on others, and enhances the reliability of the module. The module can measure 4~20ma current signal and ±5V, ±10V voltage signal, with acquisition accuracy of 0.1%. The module has 250ohms sampling resistance under current mode, and isolation voltage between channels up to 1000VDC.

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引用本文

胡中澤,靳子洋.具備HART主站功能的模擬量采集模塊設計計算機測量與控制[J].,2022,30(12):270-275.

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歷史
  • 收稿日期:2022-05-24
  • 最后修改日期:2022-06-17
  • 錄用日期:2022-06-21
  • 在線(xiàn)發(fā)布日期: 2022-12-22
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