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Mil-std-1750a instruction set is one of the common instruction sets of satellite-borne missile computer. In order to realize the universality verification of CPU+FPGA of this kind of instruction set, realize the abnormal testing of safety, strength and single particle flip, meet the requirements of test coverage and ensure the reliability of satellite-borne and missile-borne computer system,A simulation model construction method of CPU+FPGA is proposed, and a simplified 1750A simulation soft core is realized by using key technologies such as the implementation of interrupt and fault processing mechanism, floating point operation unit design, anomaly injection mechanism design and graphical control interface.Experiments show that the simulation model platform of CPU+FPGA designed by using the simulation soft core can greatly improve the verification efficiency and reliability of FPGA products related to 1750 series CPU interfaces, and also provide a test platform for convenient fault injection and clear fault location for subsequent tests of satellite-borne and missile-borne software.