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Remote control FPGA is the core part of satellite executing ground instruction and transmitting ground data, so it must be verified comprehensively to avoid potential design problems.??In this paper, remote control FPGA as the Device Under Test, using the most advanced Universal Verification Methodology UVM to establish an integrated closed-loop simulation verification platform.??The verification platform has the functions of random generation of test vector with constraint convergence and automatic checking of the correctness of output results, realizing the function coverage detection, which can effectively improve the efficiency and quality of remote control FPGA verification and better meet the verification requirements?.