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With the development of highly integrated integrated circuits and high-speed board-level printed circuits, the communication frequency between boards has reached the GHz level, and the traditional board-level circuit design scheme has been unable to popularize the circuit design of higher frequencies. Aiming at the board-level design of the high-speed SDIO bus, based on the signal integrity simulation of the Cadence Sigrity platform, a high-speed signal simulation method for the SDIO bus is proposed. This method has high simulation reference significance for the SDIO bus. Board-level circuit design and simulation optimization of embedded platform, experimental simulation of stacked structure, stacking sequence, trace length, ground via, and number of vias, optimized PCB design, researched and analyzed S-parameters and time domain diagrams, and proposed A reference method of circuit routing design of SDIO bus is presented, and the feasibility and practical value of the scheme are demonstrated through theoretical analysis and simulation experiments, which fills the blank of SDIO bus design in signal integrity simulation analysis.