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A multicycle path is a way to split complex circuit operations over multiple clock cycles to improve the clock frequency of the circuit. The error constraint of multicycle path may cause design iterations and false positives in design and verification. In this paper, the generation mechanism of multicycle path and the common problems in design and verification are classified and analyzed. A method of finding multicycle paths in design is presented by combining formal verification with static timing analysis.Firstly, through static time sequence analysis, the paths of time sequence violation are found out. Then, the designed detection circuit is inserted for these paths. By detecting the destination register sampling control signal valid time, whether the path is a multicycle path can be determined. The detection circuit is validated in the form of assertions, and multicycle paths are detected by automated means.The results show that the proposed method can detect all error multicycle paths under two clocks effectively, and avoid the error constraint of multicycle path, and omit the manual analysis to confirm the multicycle path.