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In high-reliability aerospace, avionics and military applications, radiation-induced multiple bit upset (MBU) has become a major reliability concern in FPGA memory cells. Traditional single-bit error correction (SEC) and double-bit error detection (DED) cannot provide protection against MBU fault in FPGA memory, causing memory storage failures. In order to reduce the impact of MBU, the RM(2,5) encoding is used to protect the FPGA block memory，which realizes the correction of the flip error of a single codeword less than 4 bits. The RM coding system is designed with triple module redundancy (TMR), which solves the defect that the RM code does not have radiation resistance. RM(2,5) codec module has been implemented in Xilinx Virtex-5 FPGA and the codec module runs at 225.284MHz, which only 1.33% LUT resource occupation. Theoretical analysis and hardware experiments show that the Error Detection And Correction(EDAC) system can correct errors of less than 4 bits and improve the reliability of the FPGA memory.