Abstract:In a certain type of control module based on FPGA + C8051 single-chip microcomputer architecture, serial communication bus RS232 is used to realize data interaction between FPGA and single-chip microcomputer. In order to realize the abnormal solution of the single-chip computer due to the external high-priority interrupt triggering the serial port receiving interrupt to close, resulting in the serial port receiving being opened again, the data frame is misaligned and the data frame is spliced. Research and process the duration of a complete data frame received by the microcontroller, the processing mechanism of receiving a frame of data, the mechanism of receiving data frames, etc., and set the monitoring point in the program to close the serial data frame by an external interrupt. The frequency of interrupt occurrence is monitored; it is confirmed that the factors caused by this serial data frame splicing and data frame error problem are that after the serial port reception of the microcontroller is turned on, the external high-priority interrupt is triggered to close the serial port interrupt. The FPGA control software does not stop the serial data frame transmission. After the serial port interruption of the microcontroller is restarted, the new serial data frame is spliced ??with some of the data frames received before the interruption of the microcontroller is turned off. When the data frame contains data that is consistent with the end of the data frame in the communication protocol, the frame data will be interpreted as a normal data frame, so that there is an abnormal problem of splicing and misalignment during data analysis. The monitoring signal and the corresponding test case are added to the software with abnormal communication data misalignment to capture the serial port interruption off time capture, and the result analysis and experimental verification of the serial data frame splicing are realized. After taking measures such as reducing the serial port interruption closing time for the abnormal communication data misplacement, it ensures the abnormal phenomenon of splicing and misalignment of the communication data caused by the serial port closing time when the serial data frame is received. It effectively solves the problem of data splicing caused by the serial port closing time being too long, and ensures the normal communication data between the FPGA and the single chip of the control module.
