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基于IBIS模型的多路脈沖信號源ADS仿真
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西北核技術(shù)研究院 強脈沖輻射環(huán)境模擬及效應國家重點(diǎn)實(shí)驗室

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T N 4

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國家自然科學(xué)基金面上項目(51577156)


ADS Simulation of Multi-channel pulse Signal Source Based on IBIS Model
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    摘要:

    使用高速比較器+兩級時(shí)鐘扇出buffer+比較器輸出CMOS電平方案,利用ADS的Integrity–IBIS模塊,搭建了80臺示波器用脈沖信號源。介紹了IBIS模型原理、語(yǔ)法結構及模型適用性,并進(jìn)行了瞬態(tài)仿真,分析了高速比較器IC、時(shí)鐘扇出IC和脈沖輸出IC之間的差分信號完整性,對最終輸出信號的延遲和抖動(dòng)進(jìn)行了計算。仿真結果表明:使用高速比較器+兩級時(shí)鐘扇出buffer+比較器輸出CMOS電平方案可獲得80路同步觸發(fā)信號;輸入輸出信號延遲<2.6ns,抖動(dòng)<11ps,50Ω負載時(shí)輸出信號幅值1.97V,前沿997ps,滿(mǎn)足多路示波器外觸發(fā)信號要求。

    Abstract:

    Based on the application of level scheme of CMOS with high-speed comparator, two-stage clock fan-out buffer and comparator output, the integrity-IBIS module of ADS was adopted to build up 80 oscilloscope external trigger systems . The principle, grammar structure and applicability of IBIS model was introduced, the transient simulation was carried out to analyze the integrity of differential signals between the high-speed comparator IC, clock fan-out IC and pulse output IC, and the delay and jitter of the final output signal were calculated. The results of the simulation showed that: 80 channel synchronous trigger signal could be achieved with the application of level scheme of CMOS with high-speed comparator, two-stage clock fan-out buffer and comparator output; the delay of input and output signal was less than 2.6ns and the jitter was less than 11ps, output signal amplitude was 1.97V and the leading edge was 997ps with the load of 50Ω, which met the requirements of external trigger signals of the multi-channel oscilloscope.

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周文淵,呼義翔,羅維熙,張信軍,尹佳輝.基于IBIS模型的多路脈沖信號源ADS仿真計算機測量與控制[J].,2020,28(10):270-274.

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歷史
  • 收稿日期:2020-03-13
  • 最后修改日期:2020-04-02
  • 錄用日期:2020-04-03
  • 在線(xiàn)發(fā)布日期: 2020-10-21
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