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In order to improve the problem of poor frequency division of traditional synthesizer under the influence of noise, a noise suppression frequency synthesizer for wireless satellite communication network system is designed. According to the overall architecture of the noise suppression frequency synthesizer, the voltage controlled oscillator is designed, and the MAOC-114850 chip is selected as the core of the voltage controlled oscillator. According to the LC voltage controlled oscillator principle circuit, the voltage controlled variable reactance component is inserted into the input. In the frequency original, the input control voltage and the vibration frequency are controlled, and the generated current source is within the voltage control by changing the charging rate of the capacitor. The MB506 in-line/DIP8 UHF prescaler chip is selected as the core chip of the prescaler, and the digital circuit is customized after many times of frequency division. According to the on-chip integrated design requirements of the loop filter, a third-order passive loop filter is used to improve the phase margin between the resistor and the capacitor, and to suppress noise. The control module is added to define the minimum oscillation frequency range of the voltage controlled oscillator, the frequency hopping interval is determined according to the crystal reference frequency, and the result is saved to the frequency division frequency synthesizer, thereby completing the noise suppression frequency division synthesizer design. The experimental results show that the maximum frequency division efficiency of the synthesizer can reach 98%, which provides guarantee for the stable operation of the wireless satellite communication network system.