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Three interface modes, Ports, Slave FIFO and GPIF Master, are available for CY7C68013A which is a Cypress’s USB2.0 microcontroller. In Slave FIFO mode and GPIF Master mode, the data FIFOs in the USB connect directly to outside interface. And the both mode are usually used for a peripheral which requires high-speed and real-time data transmission. On the other hand, the Port mode where CPU participate provides an effective method for a peripheral which requires low-speed and real-time or high-speed and non-real-time data transmission. Because the Port mode was less paid attention in the previous literatures, and in order to help developers to better understand the details of USB data transmission, this paper introduced the design of data transmission module in detail. This module chose the chip CY7C68013A as the core of the design. Firstly, it described the USB data transmission process. And then, it focused on communication protocol design, hardware design, firmware design, driver software design, and host application design, which are covered in the module design. Reliable data transmission between the computer and peripherals had been achieved by this module. And the test results showed that this module can meet requirements for data transmission system. This module can ensured data be transmitted reliably with the use of command/response transport protocol, and had high use value. And it had referential value for other other interface modes design.