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The common method of RS422 serial port communication realized by FPGA often encounter many problems, such as FIFO depth is incorrect, the timing of writing FIFO data port and reading FIFO data port are compete, and signal delay between multiple modules leads to FPGA metastable state, so a new method of RS422 serial port communication is proposed. This method replaces the traditional FIFO by using register array as a cyclic queue, uses the counter instead of the baud rate generation module, integrate multiple modules into one module, only one master clock, all registers share one clock with the clock input, and constraints FPGA logic and timing to avoid the FPGA metastable state. The experimental results show that the method is fast, reliable and stable. It can make the whole system more flexible and compact, reduce the whole circuit volume and improve the reliability and stability of the system.