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A single chip Mobile Display Digital Interface (MDDI) data processing circuit was implemented based on FPGA. Based on the requirements of monolithic integrated AM-OLED driver IC and deficiency of parallel data bus in mobile display device, the MDDI data processing circuit is designed. MDDI is a high-speed serial digital interface standard, since it has many advantages such as less signal lines, higher signal transmission reliability, lower power consumption and the simpler circuits, it is widely used in the mobile display terminal. This paper proposes a novel design strategy for MDDI Type2 host data processing circuit to reduce the complexity of the circuit. In this design, the internal circuits are controlled with two-stage state machines. The master state machine is used to control the state switch from the secondary machine, and the secondary machine is used for generating MDDI data. The configurable registers control the packets generated and change the interface mode. RTL code of the MDDI data processing circuit is designed using Verilog to implement the soft-core. The synthesized results by Xilinx tools show that, this data processing circuit can support AM-OLED display with 480-RGB × 320 resolution and 260k color image data, the maximum transfer rate is 180 Mbps. The performances of the MDDI data processing circuit meet the requirements of system design.