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Owing to the increasing high frequency of circuit system,it is required the performance of clock signal transmission,applying to system interconnection an circuit.To deeply analysis on a High-speed clock circuit and parameter of a signal process system can not work properly and the SRIO link error in the process of testing, we find that Thermal Noise effects for clock signals,jitter affects the SRIO link disconnection. Therefore,thesis discuss t present solution for An Design Optimization,by increasing the transition slope of the clock signal,improve clock suplly quality and reliability function,in the last,the experiment results show that the system works stably and reliably,The proposed method achieves the expected effect.