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Counter is one of the important parts of the PLC. In the automatic control system with PLC as the core component, the software can realize the real-time and accurate count of the system. Through the dual port RAM, ARM command can be transmitted to the FPGA. The FPGA control counter related operations, the FPGA oscillator frequency 50 MHz as counter control module timing constraints, counter design with addition and subtraction counting function, power holding function, data transmission function, so as to meet the needs of the PLC controller of the count, and through the use of memory address mapping the counter controller instruction execution more efficient. The communication time sequence and communication protocol of the FPGA internal control and FPGA instruction execution controller are designed. After the simulation and testing of the design, the count frequency of a single counter reaches 2 MHz, the function of the PLC counter is basically realized, and the design requirements of the stable count are achieved.