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In allusion to the requirement of timing perturbation of data transmission subsystem in spaceborne synthetic aperture radar (SAR), a new design of SAR load simulator, who is based on delay unit with FPGA primitive, is proposed in this thesis. The delay unit , who can do timing perturbation in data transmission subsystem test, consists of IODELAY primitive, and is designed by timing rules. Finally, the performance and robustness are assessed through the simulation and test, whose result shows that the range of timing perturbation is from -6ns to 6ns with 1ns step.