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PLC system based on ARM and FPGA construction, analysis the functional requirements of the PLC to the timer / counter, design can be executed in parallel timer / counter, construct the timer / counter. And shared with a single port read write data communication controller and FPGA as the central controller, timer / counter for internal work is independent of each other, parallel work. And through the timer / counter instruction operation more efficient by the use of memory address mapping. The communication between the central controller and timer / counter is designed, and the control and testing of the timer / counter is convenient. Through the simulation test, the timer / counter can satisfy the basic function of PLC timer / counter, and achieve the design requirements of the stability of timing / counting.