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The system is designed for the visible channel of the next generation of spacecraft payload. The main function of the system is to obtain real-time image of the visible channels, and complete the ground debugging and performance testing of the visible channel. This paper presents the complete design of the system, including the hardware and software, according to test requirements. In the system, a new generation of low-power Xilinx’s field programmable gate array (FPGA) is used as the control core, and programed with Verilog language from top to bottom to complete the hardware timing-driven and logic control. The main work is to complete the mechanical interface design, the timing-driven of the CMOS detectors, signal conditioning, analog to digital conversion, data transmission interface design and PC software design. High speed data transmission is achieved by using the USB interface. After testing, the system works well and can well meet the practical engineering requirements. 