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Due to the jitter of the signals into the FPGA, as well as the different signal phases and different clock regions in the FPGA, the software reliability design became important and complex as well as the circuits. It analyzed some jitter control methods of the signals and classified them, then designed a few new methods of how to deal with the jitter signals. The methods could restrain pulse-noise with different width and frequency. They improved the signal integrity and reliability by cutting down the output frequency reasonably, or making use of the primitive in FPGA. In other words, they could enhance the reliability and stability of the FPGA software. These methods were easy to implement in VHDL, and they could give a guarantee to the projects in aero-space projects and industry control regions. 