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With the development of Network-on-chip(NoC) system, the testing of NoC system has become an indispensable part. To complete the communication architecture of NoC system testing, the test model for network-on-chip communication is established at first time and then the improved technology of BIST and MATS++ algorithm is used. Using Verilog language to complete the design of testing model, the test method completed the testing of communication architecture in the NoC system based on FPGA. Experiment results show that the increase in area overhead is less than 4%,the test method has not only achieved 100% fault coverage, but also reduces testing time to the 35.2 ms.