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This paper proposed a method which employed FPGA to design PLC information output and read controller.By the control of internal timing pulse, the controller will accomplish the bit informatiom's addressing and read/write operations in storage unit with Y numbered address independently while the controller carrying out the output information command.This paper discusses the circuit composition and basic principle of the controller.Using Verilog HDL language to implement the construction and the connection of the hardware circuit.The test result shows that:while the PLC user program is running,the controller can read or write the bit information according to the command independently,making the execution of the output bit information command and other system function module in parallel operation to improve the speed of PLC instruction execution sequence, shorten the PLC scan cycle.