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This paper proposes a unified delay test architecture, in which the design resources for on-line delay fault detection can be reused to support off-line delay testing. Firstly, a stability checker, which has low hardware overhead, is presented to monitor the stability violation from each critical combinational output. Secondly, a global error generator, which is shared among stability checkers, can produce a global error signal from individual stability checkers to indicate whether a delay fault appears. Finally, a local scan enable generator is incorporated into the scan chain to support scan-based off-line delay testing. The simulation experimental results show that, Compared to the previous techniques, the proposed delay fault detection methods have much lower hardware overhead and design complexity.