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Detection of Small Delay Defects (SDDs) is a major concern in modern circuits using nanometer technologies, even when SDDs do not produce functional failures, they represent a reliability risk. The detection of these defects aggravates in the presence of process variations. In this paper, a methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is proposed. This methodology exploits the concept that for two highly correlated paths, an important part of the delay variance in one path can be described by the delay variance in the second path. In addition, a statistical timing analysis framework has been developed and implemented to compute timing information and Inter-Path Correlation (IPC), which considers the spatial and structural correlation, and random dopant fluctuations. Simulation results in 74LS85 and ISCAS85 benchmark circuits evince the feasibility of the proposed methodology.